This invention relates generally to analysis of circuit designs, and more particularly to interactively generating visualization constraints for circuit designs.
As the complexity in circuit design has increased, there has been a corresponding improvement in various kinds of verification and debugging techniques. In fact, these verification and debugging techniques have evolved from relatively simple transistor circuit-level simulation (in the early 1970s) to logic gate-level simulation (in the late 1980s) to the current art that uses Register Transfer Language (RTL)-level simulation, and formal verification. RTL describes the registers of a computer or digital electronic system and the way in which data are transferred among the combinational logic between registers.
During some of these verification techniques, a circuit design is simulated or tested against a set of properties to evaluate the operation of the circuit design. In simulation, inputs provided by a circuit designer are used to determine values for variables in the circuit design over one or more clock cycles. The values determined using the provided inputs are displayed to the circuit designer as waveforms, which may enable the circuit designer to assess whether the circuit design exhibits desired behaviors. If the designer is looking for a particular behavior of the circuit design exhibited in a waveform, the designer modifies the inputs used for simulation until the waveform shows the desired behavior. Similarly, if testing a circuit design against a set of properties, the designer modifies the properties or the circuit design until the output of the test confirms that the circuit design meets desired behaviors or demonstrates that the circuit design does not meet the desired behaviors.
Circuit designers sometimes verify a circuit design in the presence of constraints, which force the waveform to meet a certain set of conditions. During the testing of a circuit design, many different constraints may be needed before a waveform illustrates a behavior of the circuit design that is of interest to a circuit designer.